Exemplary embodiments of the present invention relate to semiconductor fabricating technology, and more particularly, to a semiconductor device which has buried bit lines and a method for fabricating the same.
Recently, in the semiconductor industry, in order to increase the degree of integration, a DRAM below 40 nm is being developed. In this regard, in the case of a planar transistor or a recessed gate transistor which is used in an 8F2 or 6F2 cell architecture where F is a minimum feature size, difficulties exist in scaling below 40 nm. Hence, a DRAM having a 4F2 cell architecture capable of improving the degree of integration 1.5˜2 times at the same scaling condition is desired, and thus, a vertical channel transistor has been proposed.
In the vertical channel transistor, an annular gate electrode is formed to surround an active pillar which extends vertically on a semiconductor substrate, and a source region and a drain region are respectively formed in the upper and lower portions of the active pillar when viewed from the gate electrode, so that a channel is defined in the vertical direction. Thus, even when the area of the transistor is reduced, a channel length is not adversely influenced.
FIGS. 1A and 1B are views illustrating a conventional semiconductor device with buried bit lines, wherein FIG. 1A is a cross-sectional view and FIG. 1B is a plan view.
Referring to FIGS. 1A and 1B, a plurality of pillar structures 200 each including a body pillar 12, a head pillar 13, a buffer layer pattern 14, a hard mask layer pattern 15 and a capping layer 16 are formed on a substrate 11.
The outer surface of the body pillar 12 is surrounded by a gate insulation layer 17 and a gate electrode 18. An impurity region is formed in the substrate 11 through impurity ion implantation to serve as a source region or a drain region and at the same time as a buried bit line 19. An interlayer dielectric 20 is filled in a trench 19A which separates adjoining bit lines 19 from each other.
Word lines 21 are formed in a direction in which they are connected with gate electrodes 18 and cross with buried bit lines 19.
In the conventional art, since the buried bit line 19 is formed by implanting impurity ions into the substrate 11, for example, a silicon substrate, the buried bit line 19 is formed in the form of not a metal layer but a silicon wiring line. Therefore, because the specific resistance of the silicon wiring line is relatively larger than that of the metal layer, a concern is raised in that the resistance of the buried bit line 19 increases.
More specifically, since not a metal layer but silicon doped with impurities is used to form the buried bit line 19, the resistance of the buried bit line 19 increases, and due to such an increase, the operating speed of the semiconductor device decreases, which raises a concern.
In order to cope with these concerns, it is desirable to enlarge a current path, designated by the reference symbol ‘I’, of the buried bit line 19 as shown in FIG. 1B, and thus the pitch of the buried bit lines 19 may increase. However, in this case, another concern is raised in that an area of a unit cell area (4F2=2F×2F) may increase.